📝 Memory allocation in contiguous memory allocation (14 MCQs)

📖 Explanation: The base register holds the lowest physical address a process may reference, establishing the start of its allowed region. This ensures the CPU cannot address memory below that point. Options B, C, and D describe unrelated concepts: the largest address is defined by the limit, the segment size is the limit value, and privilege flags are stored elsewhere. By keeping the base correct, the system enforces isolation and prevents accidental or malicious access to other memory areas.

📖 Explanation: The limit register specifies how far beyond the base address a process may go, effectively setting the maximum legal address. Without it, the CPU would have no way to know where the process's memory region ends, risking overlap with other processes. Options A, C, and D describe unrelated functions: priorities are managed by the scheduler, flags are part of status registers, and mode indication is handled by separate control bits.

📖 Explanation: The highest address equals base plus limit minus one: $300040 + 120900 - 1 = 420939$. This calculation defines the inclusive upper bound of the process's address space. Option A is off by one low, Option B exceeds the limit by one, and Option D is far beyond the allowed range. Understanding this arithmetic is crucial for ensuring a process cannot read or write outside its allocated region, which could corrupt other processes or the operating system.

📖 Explanation: The CPU compares the requested address with the base and limit; because 421000 exceeds $300040 + 120900 - 1 = 420939$, the check fails and the hardware raises a protection fault, terminating or trapping the process. Options A and C describe behaviors that would break isolation, while Option B would mask the error and lead to unpredictable results. The fault mechanism preserves system stability by preventing illegal memory accesses.

📖 Explanation: Base and limit registers implement a basic form of address translation by mapping a contiguous virtual region to a physical region, much like a single segment in segmented memory. This is a precursor to full virtual memory systems, which use more complex structures such as page tables. Options B and D incorrectly claim they remove translation mechanisms, and Option C misstates their scope to kernel memory only.

📖 Explanation: Hardware can perform address checks on every memory reference with minimal latency, avoiding the performance penalty of a software trap for each access. An OS‑level check would require context switches and additional instructions, dramatically slowing execution. Options A and D misrepresent OS capabilities, and Option C describes a function not related to protection. Fast hardware enforcement thus keeps programs running efficiently while still maintaining strict isolation.

📖 Explanation: Physical addresses are calculated by adding the logical offset to the base: $200000 + 12345 = 212345$. This simple addition respects the limit because 12345 is less than 50000, so the address is valid. Options A, B, and D are close but incorrect arithmetic results, illustrating common off‑by‑few errors. Correct translation is essential for a process to locate its data correctly within the allocated physical memory region.

📖 Explanation: Process X occupies 100000‑139999, while Process Y occupies 130000‑159999, creating an overlapping region from 130000‑139999. Therefore their spaces are not disjoint, and neither process fully contains the other. Options A, B, and C each mischaracterize the relationship, ignoring the shared interval. Overlap would allow one process to read or modify the other's data, violating protection guarantees.

📖 Explanation: When the process tries to execute instructions located beyond the defined limit, the hardware detects the violation and raises a protection fault, typically terminating the program. The OS does not silently adjust limits (Option B), and the CPU does not disregard the limit (Option C). Option D is unrealistic because memory allocation is not dynamic based on faults. This scenario highlights the importance of correctly configuring limit values during loading.

📖 Explanation: The accurate comparison is that base/limit protection offers a simple contiguous segment, whereas paging breaks memory into fixed‑size pages and uses page tables for translation. Option A reverses the correct description, Option C incorrectly claims paging removes limits, and Option D misstates the capability of a single register set to handle many processes. Recognizing these differences clarifies why modern systems favor paging for flexibility despite added complexity.

📖 Explanation: Validating limit values before they are programmed into the hardware ensures that absurdly large limits, like 0xFFFFFFFF, are rejected, preserving kernel integrity. A privilege check (Option A) controls access but does not catch malformed limits, ASLR (Option B) randomizes addresses but does not enforce size constraints, and guard pages (Option D) protect against overrun but assume the limit is already reasonable. Proper validation is the primary defense against such configuration errors.

📖 Explanation: Each memory reference triggers a comparison of the generated address against the base and limit registers, adding a small but measurable delay to every load or store operation. Options A and B describe unrelated hardware characteristics, while Option C pertains to multitasking overhead, not per‑access checks. Understanding this cost helps architects balance security with speed, especially in high‑throughput systems where many memory accesses occur.

📖 Explanation: P1 occupies 0‑49999, P2 occupies 45000‑74999, and P3 occupies 80000‑99999. The overlap between P1 and P2 (45000‑49999) is 5000 bytes. Unique memory used = 50000 (P1) + 30000 (P2) – 5000 (overlap) + 20000 (P3) = 95000 bytes, and overlap is present. Options B and D give incorrect totals, and Option C incorrectly states there is no overlap. This calculation demonstrates how overlapping segments waste memory and violate protection rules.

📖 Explanation: Base and limit registers give a straightforward, low‑overhead way to delineate a process’s address space, making address checks fast but limiting the ability to create multiple, variable‑size segments. Segmentation offers greater flexibility by allowing several segments with different attributes, but it introduces extra hardware and software complexity. Options A and D misrepresent the hardware requirements, and Option C reverses the typical security‑performance relationship. Recognizing this trade‑off helps designers choose the appropriate protection mechanism for their system goals.