📝 Logical versus physical address space in Main memory (11 MCQs)

📖 From Operating System • 8. Main Memory • 11 questions available

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What is Logical versus physical address space in Main memory?

Definition:
The logical address space is the set of virtual addresses generated by the CPU while the physical address space comprises actual memory locations accessed after translation through the MMU.

Example:
A process generates logical address $LA = 2048$ which translates to physical address $PA = LA + R$ where $R$ is the relocation register value of $5000$ yielding $PA = 7048$ .

Reason:
This separation allows programs larger than physical memory via virtual memory and provides isolation between processes preventing unauthorized access.

Easy

Medium

Hard

📝 All Logical versus physical address space in Main memory MCQs

Q1. What term describes the address generated by a program before any translation by the memory-management unit?

A.Physical address

B.Logical (virtual) address ✅

C.Physical memory location

D.Kernel address

💡 Difficulty: easy | ✅ Correct: B

📖 Explanation: Logical (virtual) addresses are the values a program produces when it references memory. The MMU later maps these to actual locations in RAM. They differ from physical addresses, which refer directly to hardware cells. This separation lets the OS relocate programs, provide isolation, and implement paging. Hence the correct answer is B. The other choices describe physical or unrelated concepts, which the MMU does not generate from program code.

Q2. A process has a base register value of $0x2000$ . If the program generates a logical address $0x0150$ , what is the corresponding physical address?

0x2150

✅

0x0150

0x2000

0x3500

💡 Difficulty: easy | ✅ Correct: A

📖 Explanation: The base register holds the start of the process’s segment in physical memory. Adding the logical offset $0x0150$ to the base $0x2000$ yields the physical address $0x2150$ . Option A reflects this calculation. Option B omits the base, option C ignores the offset, and option D adds an incorrect amount. This demonstrates how simple base‑plus‑offset translation maps a program’s virtual view to actual RAM locations.

Q3. Why does an operating system prefer using logical addresses rather than physical addresses for program code?

A.It allows programs to be relocated without modification ✅

B.It speeds up CPU execution

C.It reduces overall memory consumption

D.It eliminates the need for paging

💡 Difficulty: medium | ✅ Correct: A

📖 Explanation: Logical addresses give the OS flexibility to move code and data in RAM without changing the program itself. By translating these addresses at run time, the OS can place processes wherever free memory exists, supporting multitasking and protection. Option A states this benefit. Option B is inaccurate because translation adds overhead, option C is unrelated, and option D is false because paging is still needed for virtual memory.

Q4. Given a page size of 4 KB ( $2^{12}$ bytes) and a page‑table entry that maps virtual page 1 to physical frame 7, what physical address corresponds to the logical address $0x1234$ ?

0x7234

✅

0x1234

0x4234

0x7230

💡 Difficulty: medium | ✅ Correct: A

📖 Explanation: A 4 KB page means the lower 12 bits are the offset. The logical address $0x1234$ has page number 1 (bits above the offset) and offset $0x234$ . The page table maps page 1 to frame 7, so the physical address is frame 7 × 0x1000 + offset = $0x7000 + 0x0234 = 0x7234$ . Option A matches this result. The other options either ignore the frame mapping or mis‑calculate the offset.

Q5. Which statement best captures the primary difference between segmentation and paging memory management schemes?

A.Segmentation uses variable‑size blocks while paging uses fixed‑size pages ✅

B.Paging requires a TLB and segmentation does not

C.Segmentation provides protection bits, paging does not

D.Paging maps logical to physical addresses, segmentation does not

💡 Difficulty: medium | ✅ Correct: A

📖 Explanation: Segmentation divides a program’s address space into logical sections that can vary in size, such as code or data segments. Paging, by contrast, breaks memory into equal‑sized pages, simplifying allocation and page‑table management. Option A correctly describes this distinction. Options B, C, and D are inaccurate: both schemes can use a TLB, both provide protection, and both perform logical‑to‑physical translation.

Q6. A TLB contains entries for virtual pages 0–3. When the CPU accesses virtual page 5, what event occurs?

A.TLB hit

B.Page fault

C.TLB miss requiring a page‑table walk ✅

D.Interrupt to the kernel

💡 Difficulty: medium | ✅ Correct: C

📖 Explanation: The TLB (Translation Lookaside Buffer) caches recent virtual‑to‑physical translations. Since it only holds pages 0‑3, an access to page 5 is not cached, resulting in a TLB miss. The hardware then consults the page table to obtain the mapping, which is a page‑table walk, not a page fault. Therefore option C is correct. Option A incorrectly assumes a hit, option B confuses a miss with a fault, and option D misstates the mechanism.

Q7. How does assigning each process its own logical address space improve overall system security?

A.It prevents one process from reading or writing another's memory ✅

B.It speeds up inter‑process communication

C.It reduces the amount of RAM needed

D.It eliminates the need for context switches

💡 Difficulty: medium | ✅ Correct: A

📖 Explanation: Separate logical address spaces isolate processes, so a program cannot directly address memory belonging to another process. The MMU enforces this isolation by translating each process’s virtual addresses to distinct physical frames, and any illegal access triggers a protection fault. Option A captures this security benefit. Options B, C, and D describe unrelated effects that do not stem from address‑space isolation.

Q8. In a two‑level page table, a 16‑bit virtual address is divided into a 4‑bit first‑level index, a 4‑bit second‑level index, and an 8‑bit offset (page size $256$  bytes). The first‑level entry for index $0xA$ points to a second‑level table located at physical frame $0x300$ . The second‑level entry for index $0x5$ contains frame number $0x7C$ . What physical address corresponds to the virtual address $0xA59F$ ?

0x7C9F

✅

0x309F

0xA7C9F

0x7C00

💡 Difficulty: hard | ✅ Correct: A

📖 Explanation: The virtual address splits as: first‑level index = 0xA, second‑level index = 0x5, offset = 0x9F. The first‑level entry directs to the second‑level table; the second‑level entry gives physical frame 0x7C. The final physical address is frame 0x7C × 0x100 (page size) + offset =  $0x7C00 + 0x009F = 0x7C9F$ . Option A reflects this calculation. The other options misplace the frame or ignore the offset.

Q9. A shared library is compiled to run at base address $0x500000$ but the loader places it at $0x400000$ . If a function inside the library has a compiled offset of $0x200$ , what runtime address will the program use to call this function?

0x400200

✅

0x500200

0x300200

0x600200

💡 Difficulty: hard | ✅ Correct: A

📖 Explanation: The library’s compiled offset (0x200) is added to the actual load base (0x400000) to obtain the runtime address: $0x400000 + 0x200 = 0x400200$ . Option A shows this correct address. Option B uses the original compile‑time base, option C subtracts incorrectly, and option D adds an extra 0x200000, all of which would cause incorrect calls.

Q10. What is a key trade‑off when choosing a larger page size versus a smaller page size in a virtual‑memory system?

A.Larger pages reduce internal fragmentation but increase TLB pressure

B.Larger pages increase internal fragmentation but improve TLB coverage ✅

C.Smaller pages eliminate the need for a TLB

D.Smaller pages always improve system performance

💡 Difficulty: hard | ✅ Correct: B

📖 Explanation: Larger pages mean each page holds more data, so unused space within a page (internal fragmentation) grows, but fewer pages are needed to cover a given address range, allowing a smaller TLB to cover more memory (better TLB coverage). Option B states this balance. Option A reverses the effects, option C is false because a TLB is still useful, and option D oversimplifies performance considerations.

Q11. A process uses demand paging with three physical frames and follows the reference string: 1,2,3,4,1,2,5,1,2,3,4,5. Using the FIFO replacement policy, how many page faults occur?

A.7

B.9

C.10 ✅

D.12

💡 Difficulty: hard | ✅ Correct: C

📖 Explanation: Starting with empty frames, each new page causes a fault. After loading pages 1,2,3 (3 faults), page 4 replaces page 1 (fault), then page 1 replaces page 2 (fault), page 2 replaces page 3 (fault), page 5 replaces page 4 (fault), pages 1 and 2 hit, page 3 replaces page 5 (fault), page 4 replaces page 1 (fault), and page 5 replaces page 2 (fault). This totals 10 faults. Option C matches this count. The other numbers underestimate or overestimate the faults.

🔗 Related Topics (MCQs)

📝 Basic hardware in Main memory MCQs 📝 Address binding in Main memory MCQs 📝 Dynamic memory loading in Main memory MCQs 📝 Dynamic linking and shared libraries in Main memory MCQs 📝 Standard swapping in main memory MCQs

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