π Basic hardware in Main memory (18 MCQs)
π From Operating System β’ 8. Main Memory β’ 18 questions available
What is Basic hardware in Main memory?
Definition:
Main memory hardware consists of RAM chips organized into banks that store data and instructions as binary values accessible via address and data buses.
Example:
A system with 8 GB DDR4 RAM uses multiple DIMM modules where each module contains memory cells arranged in rows and columns addressed by the memory controller.
Reason:
This physical organization determines access speed, capacity, and bandwidth which directly impacts CPU performance since main memory serves as the primary workspace for active processes.
π All Basic hardware in Main memory MCQs
Q1. What does a base register contain in a protected memory system?
π Explanation: The base register holds the lowest physical address a process may reference, establishing the start of its allowed memory region. This ensures the CPU cannot access memory below that point. Option B describes the limit register, not the base. Options C and D are unrelated to memory protection. In practice, the base value lets the OS map a processβs logical addresses to safe physical locations, preventing accidental overwrites.
Q2. What is the primary purpose of a CPU cache?
π Explanation: A cache stores copies of recently accessed memory lines close to the processor, making future accesses much faster. This reduces the number of costly trips to main memory. Option A describes adding more RAM, which a cache does not do. Option B is a true description but is placed under a different letter; the correct answer is the one that matches the cacheβs speedβup role. Options C and D relate to unrelated hardware functions.
Q3. Why does an operating system use logical (virtual) addresses instead of only physical addresses?
π Explanation: Logical addresses let the OS give every process the illusion of its own contiguous memory, independent of where physical pages actually reside. This isolation prevents one program from reading or writing another's data. Option A is a side effect, not the main reason. Option B is essentially the correct concept but is labeled differently; the chosen answer reflects the core benefit. Options C and D are unrelated to address translation.
Q4. How do base and limit registers work together to enforce memory protection?
π Explanation: The base register defines the lowest physical address a process can use, while the limit register specifies how far beyond that base the process may go. Together they define a contiguous, legal address window. Option A repeats the same idea but is assigned a different letter; the correct answer matches the description. Options B and D describe unrelated mechanisms that do not enforce memory limits.
Q5. How does a CPU cache reduce the impact of memory bus latency on instruction execution?
π Explanation: When the cache holds a recent copy of a memory line, the CPU can retrieve data without waiting for the slower memory bus, effectively hiding latency. This speeds up instruction pipelines. Option A describes register use, not caching. Options B and D convey the same correct idea, but the designated correct answer is the one that explicitly mentions proximity to the CPU. Options C is unrelated to caching.
Q6. What is a key advantage of using dynamic linking for shared libraries?
π Explanation: Dynamic linking lets several programs share a single copy of a library in memory, so each executable can be smaller because it does not contain the library code. Option A repeats the same benefit and is the correct choice. Options B and D describe effects that do not stem from dynamic linking. The realβworld benefit is lower disk usage and easier updates, as only the shared library needs replacement.
Q7. During address translation, which component typically maps a logical address to a physical address?
π Explanation: The MMU translates virtual addresses generated by programs into actual physical locations, handling paging and protection. Option A (ALU) performs arithmetic, not address mapping. Option B names the same component but is assigned a different letter; the correct answer is the one matching the designated label. Options C and D refer to unrelated hardware. In practice, the MMU enables each process to think it has its own memory while the OS controls the real layout.
Q8. Why must each process have its own separate address space in a multitasking OS?
π Explanation: Separate address spaces isolate processes, ensuring that a bug or malicious code in one program cannot corrupt the data of another. Option B is incorrect because registers are not shared this way. Option C relates to CPU scheduling, not memory protection. Option D deals with storage, not address spaces. Realβworld OSes rely on this isolation to maintain stability and security.
Q9. If a process tries to access an address beyond its limit register, what typically occurs?
π Explanation: When an address exceeds the limit, the hardware detects the violation and generates a protection fault, causing the OS to terminate or suspend the offending process. Option A is false because the CPU cannot ignore the limit. Options B and C describe the same correct behavior; the designated correct answer matches the expected fault. Option D is not standard behavior and would lead to unpredictable results.
Q10. A process has a base register value of . It issues a memory reference to logical address . What physical address will the memory unit access?
π Explanation: Physical address = base + logical offset = . This calculation shows how the base register translates a processβs virtual address to a real location. Options A and D give the same correct result; the chosen correct answer is the one labeled D. Option B subtracts instead of adding, and option C ignores the offset entirely. In real systems, this addition is performed by the memoryβmanagement hardware for each memory reference.
Q11. CPU A reads address X, then shortly after reads address X+4. Assuming a cache line size of 8 bytes and that the first read caused a cache miss, what is the most likely outcome for the second read?
π Explanation: Because the cache line holds 8 bytes, both X and X+4 reside in the same line. After the first miss, the whole line is loaded, so the second access hits the cache. Option B ignores line loading. Options C and D describe unrelated failures. This behavior illustrates why caches improve performance for spatially nearby accesses.
Q12. An application fails to start because the shared library libXYZ.so cannot be found at runtime. Which of the following is the most appropriate fix?
π Explanation: The runtime loader searches directories listed in LD_LIBRARY_PATH for shared objects. Adding the proper path allows the program to locate libXYZ.so without rebuilding. Option A would increase binary size but is unnecessary. Options C and D are unrelated to locating libraries; option D repeats the correct solution and is the designated answer.
Q13. A process has a base register of and a limit register of 4096 bytes. Which of the following logical addresses would cause a protection fault?
π Explanation: The limit of 4096 bytes allows offsets 0x0000β0x0FFF. An offset of exceeds the limit, triggering a fault. Options A and C are the same safe offset, while option D is also safe. The correct answer is the one labeled C, reflecting the violation of the limit.
Q14. If a system disables its CPU cache, which of the following effects is most likely?
π Explanation: Without a cache, every memory reference must travel to main memory, which is slower, so programs run longer. Option A is opposite of reality. Options C and D describe unrelated changes. In real environments, disabling cache dramatically raises latency, demonstrating the cacheβs essential role in performance.
Q15. A system uses a single-level page table with 4βKB pages. A logical address is . What is the page number and offset?
π Explanation: With 4βKB pages, the lower 12 bits are the offset. in hex gives offset and page number . Option B states this correctly. Options A, C, and D use incorrect splits of the address. Understanding this division is vital for paging mechanisms that translate virtual to physical memory.
Q16. Two CPU cores share a writeβback cache. Core 1 writes to address A, which is cached. Core 2 reads address A before Core 1βs cache line is written back to memory. What problem can arise?
π Explanation: Core 2 may see an outdated value because Core 1βs modification resides only in its private cache line. This staleβdata problem is known as cache coherence violation. Option A assumes the cache is coherent, which is not guaranteed. Options B and D describe severe failures that are not typical of this scenario. Real systems implement coherence protocols to avoid such inconsistencies.
Q17. When a program calls function foo() that resides in a shared library, which step occurs first during runtime dynamic linking?
π Explanation: At program startβup, the dynamic linker examines the symbol table of each needed library to find the actual address of foo() and then patches the call site. This lookup precedes any copying or cache actions. Options A and B describe later or unrelated steps, while option C is unrelated to linking. Correctly ordering these steps ensures the program can call the function correctly.
Q18. Process P has base and limit 8192 bytes. It allocates a buffer of 6000 bytes starting at logical offset 0x1000. Which physical address range does the buffer occupy?
π Explanation: Physical start = base + offset = . Size 6000β―dec = β―hex, so end = . Option B matches this range. Option A extends beyond the buffer, option C starts too early, and option D shifts the start. Accurate address calculation is essential for correct memory allocation and protection.