📝 Segmentation hardware in Main Memory (8 MCQs)
📖 From Operating System • 8. Main Memory • 8 questions available
What is Segmentation hardware in Main Memory?
Definition:
Segmentation hardware uses a segment table stored in memory or TLB containing base address and limit for each segment validated on every memory reference.
Example:
CPU fetches segment descriptor for obtaining base and limit ; effective address checked against .
Reason:
Hardware validation ensures safety and performance by avoiding software checks on every access enabling efficient segmented memory management.
📝 All Segmentation hardware in Main Memory MCQs
Q1. What is the set of all logical addresses generated by a program called?
📖 Explanation: The correct answer is B because the collection of every address a program can produce while running is defined as its logical address space. Option A describes the set of physical addresses, not the program‑generated ones. Option C is a hardware component, not a set of addresses. Option D refers to a technique for extending memory, not the address collection. Understanding this term helps students see why a program’s view of memory can differ from the actual hardware layout.
Q2. Why is dynamic relocation using a relocation register important for modern operating systems?
📖 Explanation: The correct answer is C because the relocation register adds a constant offset to every logical address, so a program can be placed wherever free memory exists. Option A is unrelated to relocation. Option B describes memory sharing mechanisms like copy‑on‑write, not address translation. Option D is false; virtual memory is still useful. Recognizing this reason shows how systems achieve flexibility and efficient memory use.
Q3. A system’s relocation register holds the value . If a process generates the logical address , what physical address will the MMU produce?
📖 Explanation: The correct answer is A because the MMU adds the base offset to the logical address , yielding . Option B subtracts the offset incorrectly. Option C ignores the logical part, and option D fails to apply any translation. This calculation illustrates how dynamic relocation works in real hardware, reinforcing the concept that physical addresses result from simple addition of the relocation register value.
Q4. How does the memory‑management unit (MMU) typically implement execution‑time address translation?
📖 Explanation: The correct answer is D because the MMU performs translation by adding the relocation register value to each logical address during execution, effectively hard‑wiring the mapping for that process. Option A describes caching, not translation. Option B mentions a TLB, which speeds up but does not define the basic translation mechanism. Option C confuses paging with swapping. Recognizing the MMU’s role clarifies why programs can run regardless of where they are loaded.
Q5. Process A has a relocation register of and generates logical address . Process B’s register holds and generates logical address . Which physical address belongs to Process B?
📖 Explanation: The correct answer is B because Process B adds its base to the logical address , producing the physical address . Option A uses Process A’s base. Option C mixes bases incorrectly. Option D repeats A. This scenario demonstrates that each process’s relocation register uniquely determines its physical address space, preventing overlap and ensuring isolation.
Q6. What is a key difference between execution‑time binding and compile‑time binding of addresses?
📖 Explanation: The correct answer is A because execution‑time binding translates logical addresses to physical ones during run time, so the two spaces can be distinct. Compile‑time binding fixes addresses in the program, making logical and physical addresses the same. Option B reverses the need for an MMU. Option C is false; execution‑time binding works in multitasking environments. Option D incorrectly claims compile‑time addresses can change at run time. Grasping this contrast explains why modern OSes rely on dynamic relocation.
Q7. A machine uses 4 KB pages. The relocation register contains base address . A process issues logical address . What physical address results, and is it within the allocated page?
📖 Explanation: The correct answer is D because adding the base to the logical address yields physical address ; however, the option D states which is incorrect, making D actually wrong. The correct physical address is . Since the page size is 4 KB (0x1000), the offset part is within the page, so the address is valid. Option A gives the right address but incorrectly says it is within the page; it actually is. Option B has the correct address but incorrectly says it is out of bounds. Option C fails to add the base. This problem shows how relocation works with paging and how to check bounds.
Q8. A programmer writes code assuming the first byte of the program will be at logical address . The system’s relocation register is set to . Which statement best describes the effect on the program’s execution?
📖 Explanation: The correct answer is C because the code was assembled assuming a base of zero; with a relocation register of , the hardware will add that offset to every address, so the program will actually run starting at physical address . Option A ignores the offset. Option B is partially true about shifting, but the program also needs correct address references, which are already handled by the MMU, so the statement is misleading. Option D is false; the MMU uses the register. Understanding this helps students see why absolute addresses in code must match the expected base or be relocated.