📝 Example of Intel 32 Architectures (31 MCQs)

📖 Explanation: The selector is a 16‑bit value that indexes the descriptor table and contains privilege and requestor bits. Because the descriptor tables are indexed by a 13‑bit index, the selector fits in 16 bits, leaving room for the TI and RPL fields. The other choices describe sizes that are not used for selectors, so they are incorrect. Understanding selector width helps when writing assembly that loads segment registers.

📖 Explanation: CS (Code Segment) register always points to the segment that contains the currently executing instructions. DS, ES, and SS reference data, extra, and stack segments respectively, and they do not affect instruction fetch. Recognizing the role of CS is essential for addressing code correctly, especially when performing far jumps or calls that change both segment and offset.

📖 Explanation: A segment can be as large as the full 32‑bit address space, i.e., $2^{32}$ bytes, which equals 4 GB. The limit field can be set to its maximum value, allowing the segment to span the entire linear address range. The other options are smaller fractions of the address space and therefore do not represent the maximum possible segment size.

📖 Explanation: Segmentation lets programmers think in terms of modules such as code, stack, or data, assigning each a name and offset, which matches the programmer’s view of memory. Paging then breaks the linear address space into uniform 4 KB pages, allowing the OS to manage physical memory efficiently and enforce protection at a finer granularity. The combination offers both conceptual clarity and practical flexibility, unlike the other choices.

📖 Explanation: When a far call targets a code segment, the CPU checks that the segment’s DPL is less than or equal to the caller’s CPL to prevent less‑privileged code from jumping into more‑privileged code without proper checks. If DPL > CPL, the call is blocked, preserving security. The other options misinterpret the direction of the privilege comparison or ignore the check entirely.

📖 Explanation: When every segment spans the full 4 GB, the offset inside the segment is effectively the same as the linear address, eliminating the need for segment‑to‑linear translation. This simplifies programming and compiler design. While page alignment and private stacks are useful, they are not direct consequences of a flat model, and 16‑bit real‑mode instructions are unrelated.

📖 Explanation: The data segment (often called .data) is allocated for global and static variables that have a defined lifetime for the duration of the program. The code segment holds executable instructions, the stack segment is used for function call frames, and the heap segment serves dynamic allocation. Confusing these segments leads to incorrect memory accesses, especially when using far pointers.

📖 Explanation: The limit field tells the CPU the highest valid offset within the segment, preventing accesses beyond the segment’s intended range. The selector is a separate register value, privilege level is encoded in the DPL bits, and the type bits identify whether the segment holds code or data. Misunderstanding the limit can cause segmentation faults.

📖 Explanation: The processor looks up the segment selector to obtain the base address, then adds the offset, producing a linear address. The limit is verified to ensure the offset does not exceed the segment size. Multiplying by 16 applies only to real‑mode segment:offset calculations, not protected mode, and ignoring the segment would defeat segmentation entirely.

📖 Explanation: Separating heap and stack isolates dynamically allocated memory from automatic variables, reducing the risk that a runaway pointer corrupts the call stack. Although both can be mapped with the same page tables, keeping them in distinct segments simplifies protection checks. The CPU does not mandate separate selectors, and 64‑bit registers are unrelated to IA‑32 segmentation.

📖 Explanation: The linear address is calculated by adding the base (0x00400000) to the offset (0x2000), yielding 0x00402000. The limit of 0x0000FFFF permits offsets up to 65535, so the offset 0x2000 is within bounds. The other alternatives either ignore the base or misuse the selector value, leading to incorrect addresses.

📖 Explanation: The TSS contains saved values for all segment registers, allowing the CPU to restore the complete execution context of the new task. This includes code, data, extra, stack, and other segment registers. General‑purpose registers are also stored in the TSS but are not segment registers; they are restored by the task‑switch mechanism as well.

📖 Explanation: The CPU detects that the offset exceeds the segment’s limit and raises a General Protection Fault (exception 13). A Page Fault occurs only when paging translation fails, Segment Not Present is raised when the descriptor’s present bit is clear, and Invalid Opcode is unrelated to address limits.

📖 Explanation: The type field tells the CPU if the segment contains executable code or writable data, influencing permission checks such as execute‑only or read‑only. The base and limit are stored in separate fields, and privilege level is encoded elsewhere. Without the correct type, the processor could allow illegal operations, compromising security.

📖 Explanation: The GDT resides in a fixed location and contains descriptors that are common to all tasks, such as code, data, and system segments. Individual tasks use the Local Descriptor Table (LDT) for private descriptors. The GDT can hold up to 8192 entries, far more than 8, and it is mandatory for protected‑mode operation.

📖 Explanation: The second function’s offset (0x11000) exceeds the segment limit (0x0FFFF), so the CPU detects the violation and triggers a General Protection Fault. Even though both functions reside in the same logical segment, the limit prevents the out‑of‑range offset. The other options either ignore the limit or misinterpret the fault type.

📖 Explanation: When a segment selector references a descriptor whose present bit is 0, any attempt to use that segment causes a Segment Not Present exception (interrupt 11). The General Protection Fault deals with privilege or limit violations, while a Page Fault relates to paging, and Invalid Opcode is unrelated to segment presence.

📖 Explanation: When G = 1, the 20‑bit limit field is multiplied by 4096 (4 KB), allowing segments larger than 1 MB. If G = 0, the limit is taken as a byte count. The flag does not affect executability or operand size, which are controlled by other descriptor bits.

📖 Explanation: A far call transfers control to a new segment and offset, requiring the CALL instruction with a far pointer operand. Near calls only modify the offset within the current segment. Using a near form would keep the existing segment, leading to incorrect execution. The same reasoning applies to JMP, but the question asks specifically about invoking a function, so CALL is appropriate.

📖 Explanation: A 2 MB segment equals $2 \times 1024 \text{KB} = 2048 \text{KB}$. Dividing by the 4 KB page size gives $2048 / 4 = 512$ pages. The other numbers result from incorrect division or mis‑interpreting the segment size.

📖 Explanation: Segment registers point to the base of code, data, stack, and extra segments, which are essential for locating memory references after the switch. The instruction pointer (EIP) and flag register are saved separately, and floating‑point operations use the x87/MMX registers, not segment registers.

📖 Explanation: In a flat model, each segment selector typically points to a descriptor whose base is 0, making logical and linear addresses identical. Distinct bases are unnecessary, and selectors are still 16‑bit values, not 32‑bit. The CPU still uses the selector to locate the descriptor, even if the base is the same.

📖 Explanation: A descriptor marked as read‑only data permits reads but not writes; attempting to store data triggers a General Protection Fault. Reads are allowed, executing code is prohibited by the type (code segments are needed for execution), and loading the selector is allowed as long as the descriptor is present.

📖 Explanation: A far jump supplies both a new segment selector and a new offset, causing the CPU to load CS with the selector and EIP with the offset. The other registers stay unchanged unless the target code modifies them. Swapping CS and DS does not happen automatically.

📖 Explanation: When G = 1, the 20‑bit limit is multiplied by 4096 (4 KB) and the resulting value is added to 4095 to get the highest byte address. This yields $0xFFFFF \times 4096 + 4095 = 0xFFFFFFFF$, the top of the 32‑bit address space. The other options either omit the added 4095 or treat the limit as a byte count.

📖 Explanation: The PUSH operation decrements ESP before storing the value. Decrementing from 0x1000 to 0x0FFC moves ESP within the segment limit, but the initial ESP value already exceeds the limit, so the CPU raises a General Protection Fault before the push can complete. The other options ignore the limit violation.

📖 Explanation: Because the second function’s offset (0x12000) exceeds the segment limit (0x0FFFF), a near call would violate the limit and trigger a General Protection Fault. The proper solution is to use a far call that switches to a selector whose descriptor encompasses the target offset, or adjust the limit. Changing the base does not affect the offset limit.

📖 Explanation: If paging is enabled and the linear address lacks a valid page‑table entry, the CPU raises a Page Fault (interrupt 14). This is distinct from a General Protection Fault, which deals with segment violations, and Segment Not Present, which concerns descriptor presence. Invalid Opcode is unrelated to memory translation.

📖 Explanation: Clearing the Executable bit marks the segment as data‑only, preventing the CPU from fetching instructions from it. The Writable bit controls write permissions, the Present bit indicates whether the descriptor is valid, and the Granularity flag affects limit scaling, none of which directly stop execution.

📖 Explanation: The logical address resolves to linear 0x0040FFFE, which is less than base + limit (0x0040FFFF). Therefore the access is permitted. The other fault types would only occur if the offset exceeded the limit or if paging denied the page.

📖 Explanation: Loading an invalid selector triggers a Segment Not Present exception, which can be used by operating systems to detect erroneous selectors or to implement certain protection mechanisms. The CPU does not ignore the error, nor does the selector become a general‑purpose register, and it does not switch modes.