🏠 Home > An Introduction To Microprocessor 8085 > 11. Programmable Interrupt Controller: 8259 > Interrupt Modes of 8259A
← Back to 11. Programmable Interrupt Controller: 8259

📝 Interrupt Modes of 8259A

📖 From An Introduction To Microprocessor 8085 • 11. Programmable Interrupt Controller: 8259 • 3 questions available

Practice MCQs for Interrupt Modes of 8259A. Test your knowledge with carefully crafted questions across easy, medium, and hard difficulty levels.

🔄 Last updated: 2026-07-30

1
Easy Questions
1
Medium Questions
1
Hard Questions

📝 Sample Questions

Q1. A system designer wants to generate periodic interrupts using counter 0 of the 8253. Which pin must be connected to the interrupt request line of the 8259A to ensure the interrupt is triggered?

🔹 A. CLK0 (Pin 9)
🔹 B. OUT0 (Pin 10)
🔹 C. GATE0 (Pin 11)
🔹 D. CS (Pin 21)

💡 Difficulty: easy | ✅ Correct: B

Q2. Which combination of control signals CS, RD, WR, A1, and A0 causes the 8253 to write a mode word into its mode register?

🔹 A. CS=0, RD=0, WR=1, A1=1, A0=1
🔹 B. CS=0, RD=1, WR=1, A1=0, A0=0
🔹 C. CS=0, RD=1, WR=0, A1=1, A0=1
🔹 D. CS=1, RD=0, WR=0, A1=0, A0=0

💡 Difficulty: medium | ✅ Correct: C

Q3. During configuration of the 8259A in level‑triggered mode, a designer keeps pin GATE2 low while also enabling counter 2. What is the most likely result on interrupt generation from counter 2?

🔹 A. Counter 2 will never generate an interrupt request.
🔹 B. Counter 2 will continuously assert the interrupt request.
🔹 C. Counter 2 will generate an interrupt only after a system reset.
🔹 D. There will be no effect on interrupt generation.

💡 Difficulty: hard | ✅ Correct: B

⬆️ View all questions in the quiz below

🔗 Related Topics

📝 Programmable Interrupt Controller 8259📝 Block Diagram of 8259📝 Interfacing of 8259A with 8085A📝 Vectoring Data Formats for 8259📝 Initialization of 8259
🚀 Start Quiz 📝 Practice Mode