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πŸ“ Block Diagram of 8259

πŸ“– From An Introduction To Microprocessor 8085 β€’ 11. Programmable Interrupt Controller: 8259 β€’ 27 questions available

Practice MCQs for Block Diagram of 8259. Test your knowledge with carefully crafted questions across easy, medium, and hard difficulty levels.

πŸ”„ Last updated: 2026-07-30

4
Easy Questions
15
Medium Questions
8
Hard Questions

πŸ“ Sample Questions

Q1. Which pin is designated as the ground terminal on the 8253 device?

πŸ”Ή A. Pin10
πŸ”Ή B. Pin12
πŸ”Ή C. Pin14
πŸ”Ή D. Pin16

πŸ’‘ Difficulty: easy | βœ… Correct: B

Q2. A CPU wants to load a new count into counterβ€―0. Which combination of control signals must be asserted?

πŸ”Ή A. CSβ€―=β€―0, WRβ€―=β€―0, A1β€―=β€―0, A0β€―=β€―0
πŸ”Ή B. CSβ€―=β€―0, RDβ€―=β€―0, A1β€―=β€―0, A0β€―=β€―1
πŸ”Ή C. CSβ€―=β€―1, WRβ€―=β€―0, A1β€―=β€―1, A0β€―=β€―0
πŸ”Ή D. CSβ€―=β€―0, RDβ€―=β€―1, WRβ€―=β€―1, A1β€―=β€―0, A0β€―=β€―0

πŸ’‘ Difficulty: medium | βœ… Correct: A

Q3. Design a 24‑bit timer by cascading three 8253 counters. Which pins must be connected together to achieve proper chaining?

πŸ”Ή A. OUT0 to GATE1, OUT1 to GATE2, CLK0 to CLK1, CLK1 to CLK2
πŸ”Ή B. GATE0 to CLK1, GATE1 to CLK2, OUT2 to CS
πŸ”Ή C. OUT0 to GATE1, OUT1 to GATE2, CLK0 to CLK0, CLK1 to CLK1
πŸ”Ή D. OUT0 to GATE1, OUT1 to GATE2, CLK0 to GATE0, CLK1 to GATE1

πŸ’‘ Difficulty: hard | βœ… Correct: A

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πŸ”— Related Topics

πŸ“ Programmable Interrupt Controller 8259πŸ“ Interfacing of 8259A with 8085AπŸ“ Vectoring Data Formats for 8259πŸ“ Initialization of 8259πŸ“ Initialization Command Words(ICWs) of 8259
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