📝 Multicore Processors in Multiple Processor Scheduling (43 MCQs)

📖 From Operating System • 6. CPU Scheduling • 43 questions available

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What is Multicore Processors in Multiple Processor Scheduling?

Definition:
Multicore scheduling manages threads across multiple cores on a single chip, considering shared resources like L3 cache and memory bandwidth alongside core-level parallelism with $c$ cores per socket.

Example:
The scheduler places sibling threads of a parallel application on cores sharing an L2 cache to maximize data reuse, avoiding cross-socket communication when possible.

Reason:
Multicore architectures introduce hierarchical resource sharing that naive scheduling ignores; topology-aware placement optimizes cache utilization and reduces interconnect contention for better scalability.

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📝 All Multicore Processors in Multiple Processor Scheduling MCQs

Q1. What defines a multicore processor?

A.Multiple physical processor chips connected via a bus

B.Multiple processor cores placed on the same physical chip ✅

C.A single processor core with hyper-threading technology

D.Multiple processors sharing a single memory controller

💡 Difficulty: easy | ✅ Correct: B

📖 Explanation: A multicore processor integrates multiple independent processing units (cores) onto a single physical chip. This design improves performance and reduces power consumption compared to traditional multi-chip SMP systems, while each core appears as a separate physical processor to the operating system.

Q2. How does a multicore processor appear to the operating system?

A.As a single, more powerful processor

B.As multiple separate physical processors ✅

C.As a single processor with multiple logical threads

D.As a single processor with increased cache memory

💡 Difficulty: easy | ✅ Correct: B

📖 Explanation: Each core in a multicore processor maintains its own architectural state. This makes each core indistinguishable from a traditional physical processor from the operating system's perspective, allowing the OS to schedule processes across multiple available cores.

Q3. What is a memory stall in the context of processor architecture?

A.A physical failure of the RAM module

B.A situation where the processor waits for data from memory ✅

C.A software lock that prevents memory access

D.A condition where the memory bus is overloaded

💡 Difficulty: easy | ✅ Correct: B

📖 Explanation: A memory stall occurs when the processor requests data from memory and experiences a delay while waiting for that data to become available. This is often caused by a cache miss, where the required data is not in the processor's fast cache memory.

Q4. What is the primary purpose of implementing multithreaded processor cores?

A.To increase the processor's clock speed

B.To reduce the time a core is idle due to memory stalls ✅

C.To eliminate the need for cache memory

D.To allow multiple operating systems to run on one core

💡 Difficulty: easy | ✅ Correct: B

📖 Explanation: The primary purpose of multithreaded cores is to hide memory latency. When one hardware thread is stalled waiting for memory, the core can quickly switch to another thread, keeping the processing unit busy and improving overall throughput.

Q5. In a multithreaded multicore system, what is a logical processor?

A.A virtual machine running on the system

B.A hardware thread as seen by the operating system ✅

C.A software thread scheduled by the OS

D.A core that is logically turned off

💡 Difficulty: easy | ✅ Correct: B

📖 Explanation: A logical processor is the operating system's view of a hardware thread. Each hardware thread within a core can execute a separate software thread, so the OS sees each hardware thread as an independent processor capable of running its own tasks.

Q6. A system has a dual-core processor with two hardware threads per core. How many logical processors are presented to the operating system?

A.Two

B.Four ✅

C.Six

D.Eight

💡 Difficulty: easy | ✅ Correct: B

📖 Explanation: The number of logical processors is calculated by multiplying the number of cores by the number of hardware threads per core. In this case, 2 cores * 2 hardware threads/core results in 4 logical processors, which the OS will see as 4 CPUs.

Q7. Which type of multithreading switches between threads only when a long-latency event, such as a memory stall, occurs?

A.Fine-grained multithreading

B.Coarse-grained multithreading ✅

C.Simultaneous multithreading

D.Hardware multithreading

💡 Difficulty: easy | ✅ Correct: B

📖 Explanation: Coarse-grained multithreading is characterized by thread switching occurring only in response to significant, long-latency events like a cache miss or an I/O request. The processor executes a single thread continuously until such an event causes a stall and a switch.

Q8. Which type of multithreading switches between threads at the boundary of an instruction cycle?

A.Coarse-grained multithreading

B.Simultaneous multithreading

C.Time-sliced multithreading

D.Fine-grained multithreading ✅

💡 Difficulty: easy | ✅ Correct: D

📖 Explanation: Fine-grained multithreading involves a very rapid, often cycle-by-cycle, interleaving of instructions from multiple threads. This occurs at a much finer granularity than coarse-grained multithreading, typically at the instruction cycle boundary.

Q9. What is a key characteristic of the context switch cost in fine-grained multithreading compared to coarse-grained multithreading?

A.It is higher because the pipeline must be flushed

B.It is lower because the architecture includes logic for switching ✅

C.It is the same for both types

D.It is unpredictable and depends on the workload

💡 Difficulty: easy | ✅ Correct: B

📖 Explanation: In fine-grained multithreading, the hardware is specifically designed to handle rapid thread switches. The architectural logic for switching is built in, which minimizes the overhead and makes the context-switch cost relatively small compared to coarse-grained approaches.

Q10. On a multithreaded multicore processor, how many levels of scheduling are involved?

A.One: the operating system schedules software threads to the cores

B.Two: the operating system schedules software threads and the core schedules hardware threads ✅

C.Three: the OS schedules, the core schedules, and the hypervisor schedules

D.None: the hardware handles all scheduling automatically

💡 Difficulty: easy | ✅ Correct: B

📖 Explanation: There are two distinct levels: the operating system schedules software threads onto the available logical processors (hardware threads), and a separate, often hardware-based, scheduling mechanism on the core decides which hardware thread gets to execute on the core itself.

Q11. In a dual-threaded core, what happens when one hardware thread experiences a memory stall?

A.The entire processor core halts until the data arrives

B.The core switches to executing the other hardware thread ✅

C.The stalled thread is terminated by the operating system

D.The core increases its clock speed to fetch data faster

💡 Difficulty: medium | ✅ Correct: B

📖 Explanation: When a hardware thread stalls on a memory operation, the core can immediately switch to the other hardware thread. This keeps the execution pipeline of the core busy, effectively hiding the memory latency and improving overall utilization, as illustrated by the interleaved execution model.

Q12. A processor is described as having 16 cores per chip and 8 hardware threads per core. How many logical processors will the operating system detect?

A.8

B.16

C.128 ✅

D.256

💡 Difficulty: medium | ✅ Correct: C

📖 Explanation: The number of logical processors is the product of the number of cores and the number of hardware threads per core. For a system with 16 cores, each having 8 hardware threads, the OS will see 16 * 8 = 128 logical processors available for scheduling tasks.

Q13. What is the primary cause of a memory stall in a modern processor?

A.A hardware interrupt request

B.A read or write to a memory address that is not in the cache ✅

C.A division-by-zero arithmetic error

D.A page fault that requires disk access

💡 Difficulty: medium | ✅ Correct: B

📖 Explanation: A memory stall is typically triggered when the processor attempts to access data that is not present in its cache (a cache miss). The processor then has to wait for the data to be fetched from main memory, which is a significantly slower operation, causing a stall.

Q14. How do multithreaded cores help mitigate the problem of memory stalls?

A.By increasing the size of the cache memory

B.By pre-fetching data into the cache before it is needed

C.By allowing the core to execute another thread while one waits for memory ✅

D.By using faster, more expensive RAM modules

💡 Difficulty: medium | ✅ Correct: C

📖 Explanation: Multithreaded cores provide a solution by swapping to a different hardware thread. When one thread is stalled waiting for data, the core can context-switch to another ready thread. This keeps the core's execution units active and improves throughput, effectively masking the latency of the stall.

Q15. Which of the following is a valid example of a hardware scheduling strategy for a multithreaded core?

A.First-Come, First-Served algorithm

B.Shortest-Job-First algorithm

C.Round-robin algorithm ✅

D.Priority inheritance algorithm

💡 Difficulty: medium | ✅ Correct: C

📖 Explanation: The UltraSPARC T3 processor is specifically mentioned as using a simple round-robin algorithm to schedule its eight hardware threads across the core. This is a fair, hardware-level strategy that ensures each hardware thread gets a regular slice of the core's execution time.

Q16. In the context of a multithreaded core, what does 'coarse-grained' refer to?

A.Switching threads at the very beginning of execution

B.Switching threads when a long-latency event occurs ✅

C.Switching threads every single instruction

D.Switching threads based on user input

💡 Difficulty: medium | ✅ Correct: B

📖 Explanation: 'Coarse-grained' refers to the granularity at which thread switching occurs. The switch happens at a 'coarse' interval, not frequently, and is typically triggered by a major event like a memory stall that makes the current thread unable to proceed, not by a timer or instruction cycle.

Q17. What is a major disadvantage of coarse-grained multithreading?

A.It is difficult to implement in hardware

B.It does not help with memory stall latency

C.It requires a separate cache for each thread

D.It has a high context-switch cost due to pipeline flushing ✅

💡 Difficulty: medium | ✅ Correct: D

📖 Explanation: The main disadvantage is the high cost of switching. Because the switch happens infrequently and in response to a stall, the pipeline must be flushed of the old thread's instructions before the new one can start, causing a significant performance penalty each time a switch occurs.

Q18. What is a major advantage of fine-grained multithreading compared to coarse-grained?

A.It does not require any hardware support

B.It has a very low context-switch cost ✅

C.It is easier to implement in the operating system

D.It switches threads only on a timer interrupt

💡 Difficulty: medium | ✅ Correct: B

📖 Explanation: The primary advantage is the low context-switch overhead. Because the hardware is designed for rapid switching, often at each instruction boundary, the cost of changing which thread is executing is minimal, allowing for a very fine balance of execution between threads.

Q19. On a dual-threaded core, if thread 0 is executing compute instructions and thread 1 is waiting for memory, what is the core's current execution state?

A.Executing thread 0 only ✅

B.Executing thread 1 only

C.Stalled and waiting for memory

D.Executing both threads simultaneously

💡 Difficulty: medium | ✅ Correct: A

📖 Explanation: In a standard dual-threaded core, only one hardware thread executes at a time. If thread 0 is using the core for computation and thread 1 is stalled on memory, the core will be actively executing thread 0. It will switch to thread 1 only when thread 0 also stalls or is otherwise unable to proceed.

Q20. Why might a hardware designer choose coarse-grained over fine-grained multithreading?

A.Coarse-grained provides better throughput for all workloads

B.Fine-grained requires more complex architectural logic ✅

C.Coarse-grained has no context-switch overhead

D.Fine-grained is not compatible with modern operating systems

💡 Difficulty: medium | ✅ Correct: B

📖 Explanation: While fine-grained multithreading offers lower latency, it requires more complex hardware logic to manage thread switching at the instruction cycle level. A designer might choose the simpler, less power-hungry coarse-grained approach if the workload benefits from it.

Q21. A user reports that a computationally intensive single-threaded application runs slower on a new 4-core processor than on an older single-core processor. What is the most plausible explanation?

A.The new processor has a slower clock speed

B.The single-threaded application is not utilizing the other cores ✅

C.The new processor has less cache memory

D.The old processor used a more efficient algorithm

💡 Difficulty: medium | ✅ Correct: B

📖 Explanation: A single-threaded application can only run on one core. If the per-core performance of the new processor is similar or slightly lower, the application will not benefit from the additional cores. The other three cores would remain idle or used by other processes, but the application's performance is bound to a single core.

Q22. In a scenario where a core has two hardware threads, one is performing a complex floating-point calculation, and the other is stalled on a cache miss. What can the core's scheduling logic do to improve efficiency?

A.Pause the stalled thread permanently

B.Switch to execute the floating-point calculation thread ✅

C.Pre-fetch data for the floating-point thread

D.Increase the priority of the stalled thread

💡 Difficulty: medium | ✅ Correct: B

📖 Explanation: The core can keep the execution units busy by allowing the thread that is making progress (the floating-point calculation) to continue running. While the other thread is stalled and cannot proceed, there is no benefit to executing it; the core should focus on the thread that can use the processing resources.

Q23. An architecture uses an urgency value from 0 to 7 for thread selection. What does a value of 7 typically represent?

A.The thread is blocked and cannot execute

B.The thread is of the lowest priority

C.The thread has the highest urgency to execute ✅

D.The thread is a system-level background process

💡 Difficulty: medium | ✅ Correct: C

📖 Explanation: In the Intel Itanium's urgency-based system, a value of 7 represents the highest urgency. This indicates that the thread has a high need to execute, and the hardware scheduling logic will likely select it over threads with lower urgency values when a scheduling event occurs.

Q24. The Intel Itanium identifies five specific events that may trigger a thread switch. What is the main purpose of this event-driven approach?

A.To reduce the power consumption of the core

B.To allow the OS to control the thread switch logic

C.To make thread scheduling more efficient and responsive ✅

D.To simplify the core's instruction pipeline design

💡 Difficulty: medium | ✅ Correct: C

📖 Explanation: An event-driven approach triggers scheduling decisions only when necessary (e.g., on a memory stall). This is a more efficient and responsive method than a purely timer-based approach, as it allows the core to react quickly to stalls and other events that affect thread execution.

Q25. What is the fundamental difference between the scheduling performed by the OS and the scheduling performed by the core on a multithreaded multicore processor?

A.The OS schedules software threads; the core schedules hardware threads ✅

B.The OS schedules hardware threads; the core schedules software threads

C.They both schedule software threads using different algorithms

D.The OS schedules processes; the core schedules both processes and threads

💡 Difficulty: hard | ✅ Correct: A

📖 Explanation: The OS is responsible for scheduling the higher-level software threads onto the available logical processors (hardware threads). The core, meanwhile, has a lower-level scheduling mechanism to decide which of its hardware threads will execute on the physical core at any given time.

Q26. A system uses fine-grained multithreading. A context switch occurs between thread A and thread B. What is the most likely cost of this operation?

A.Approximately the same as a page fault

B.A few cycles, as the hardware handles the switch ✅

C.Milliseconds, due to saving and restoring register states

D.Seconds, as the system must reload the entire cache

💡 Difficulty: hard | ✅ Correct: B

📖 Explanation: In fine-grained systems, the hardware is designed to switch threads with very low latency. The architectural logic for thread switching is baked into the core, so the cost is minimal, often just a few cycles, compared to the high cost of a software-based context switch.

Q27. A software developer is optimizing an application for a system with 4 cores and 2 hardware threads per core. The application uses 8 software threads. How many of these threads can execute *concurrently* at the hardware level?

A.2

B.4

C.8 ✅

D.16

💡 Difficulty: hard | ✅ Correct: C

📖 Explanation: The number of logical processors is 4 cores * 2 hardware threads/core = 8 logical processors. Each logical processor can execute a software thread, so the system can execute 8 software threads concurrently at the hardware level, providing true hardware parallelism for the application's threads.

Q28. On a system with a multithreaded core, which of the following contributes most to hiding memory latency from the perspective of a single software thread?

A.The size of the L3 cache

B.The operating system's scheduling quantum

C.The presence of another hardware thread to switch to ✅

D.The processor's clock frequency

💡 Difficulty: hard | ✅ Correct: C

📖 Explanation: While larger caches and higher clock speeds help, the key mechanism for hiding memory stall latency from a software thread is the hardware's ability to switch to another thread during the stall. This prevents the entire core from becoming idle, though the original thread will still be delayed.

Q29. A system designer is choosing between coarse-grained and fine-grained multithreading for a new processor. If the primary workload is a set of long-running, compute-intensive threads that rarely cause cache misses, which type would likely provide the best performance?

A.Fine-grained, as it has lower context-switch overhead

B.Coarse-grained, as the switching overhead would be minimal ✅

C.Fine-grained, as it can execute multiple threads faster

D.Coarse-grained, as it is more power-efficient

💡 Difficulty: hard | ✅ Correct: B

📖 Explanation: For workloads with few memory stalls, coarse-grained multithreading is better. Since context switches are rare (only on long-latency events), the high cost of a switch is rarely paid. The simplicity of coarse-grained hardware is a benefit without the downside of frequent, unnecessary switches.

Q30. Consider the Intel Itanium's urgency-based scheduling. An event occurs that triggers a thread switch. Thread A has urgency 3, and Thread B has urgency 6. Which thread will the core likely select?

A.Thread A, because lower urgency indicates a higher need

B.Thread B, because it has a higher urgency value ✅

C.Neither, the core will continue with the current thread

D.The OS will decide, not the hardware

💡 Difficulty: hard | ✅ Correct: B

📖 Explanation: The Itanium's logic selects the thread with the highest urgency value. A value of 6 is considered higher urgency than 3, meaning it is more important for that thread to execute. This hardware-level policy prioritizes threads that are deemed more critical or in need of execution.

Q31. An operating system reports 8 logical processors to a user. What is the minimum hardware configuration that could produce this result?

A.8 single-threaded cores on 8 physical chips

B.4 dual-threaded cores on a single chip

C.2 quad-threaded cores on a single chip

D.All of the above configurations are possible ✅

💡 Difficulty: hard | ✅ Correct: D

📖 Explanation: The number of logical processors is the product of cores and hardware threads. 8 cores * 1 thread = 8 logical processors. 4 cores * 2 threads = 8 logical processors. 2 cores * 4 threads = 8 logical processors. All these configurations result in 8 logical processors, demonstrating that the logical count doesn't define the underlying physical hardware.

Q32. What is the primary reason that operating system scheduling algorithms, such as those described in general CPU scheduling, can be applied to multithreaded multicore processors?

A.Because multicore processors are just like traditional SMP systems

B.Because the OS schedules software threads to logical processors ✅

C.Because the OS can directly control the hardware threads

D.Because scheduling is only done by the hardware

💡 Difficulty: hard | ✅ Correct: B

📖 Explanation: The OS's view of the system is through logical processors. Since each hardware thread appears as a logical processor, the OS can apply its existing scheduling algorithms to choose which software thread to run on each logical processor. The hardware-level scheduling is separate and transparent to the OS.

Q33. The UltraSPARC T3 uses a round-robin algorithm to schedule hardware threads. What is the primary advantage of a round-robin algorithm in this hardware context?

A.It ensures the highest-priority thread always runs first

B.It is simple to implement in hardware and provides fairness ✅

C.It guarantees the best throughput for compute-intensive tasks

D.It minimizes context switches

💡 Difficulty: hard | ✅ Correct: B

📖 Explanation: Round-robin is a simple, fair algorithm. In hardware, its implementation is straightforward. It ensures that each of the eight hardware threads gets a regular slice of the core's processing time, preventing any single thread from being starved in the long run.

Q34. In the context of a memory stall, what is the 'compute cycle' in Figure 6.10 referring to?

A.A cycle where the processor is calculating results ✅

B.A cycle where the processor is waiting for data

C.A cycle where the processor is accessing cache memory

D.A cycle where the processor is writing back to memory

💡 Difficulty: medium | ✅ Correct: A

📖 Explanation: The 'C' in the diagram represents a compute cycle, a period where the processor is performing useful computational work without waiting for external data. These are the cycles where actual instruction execution happens, contrasted with the 'M' (memory stall) cycles where the processor is idle.

Q35. What does 'M' represent in Figure 6.10, illustrating a memory stall?

A.A cycle where the processor is in a machine check

B.A cycle where the processor is moving data to registers

C.A cycle where the processor is waiting for memory access ✅

D.A cycle where the processor is processing a matrix operation

💡 Difficulty: medium | ✅ Correct: C

📖 Explanation: The 'M' represents a memory stall cycle. This is when the processor has requested data from memory and is idle, waiting for that data to be returned. These cycles represent wasted time where the processor is capable of work but is blocked on memory latency.

Q36. Based on the text, what is an approximate percentage of time a processor can spend waiting for memory?

A.10 percent

B.25 percent

C.50 percent ✅

D.75 percent

💡 Difficulty: medium | ✅ Correct: C

📖 Explanation: The text notes that a processor can spend up to 50 percent of its time waiting for data to become available from memory. This significant idle time is the primary motivation for implementing hardware multithreading to keep the core busy.

Q37. How does the cost of switching between threads in coarse-grained multithreading compare to fine-grained multithreading?

A.The cost is lower in coarse-grained multithreading

B.The cost is higher in coarse-grained multithreading ✅

C.The cost is exactly the same in both

D.The cost is variable and not related to the multithreading type

💡 Difficulty: medium | ✅ Correct: B

📖 Explanation: The cost is higher in coarse-grained multithreading. Because switches occur less frequently, the system must flush the entire instruction pipeline before loading a new thread, which is a comparatively expensive operation. Fine-grained architectures are designed to make this switch almost free.

Q38. What architectural feature is required for fine-grained multithreading that is not necessary for coarse-grained multithreading?

A.A larger cache memory

B.A second set of registers

C.Specific hardware logic for rapid thread switching ✅

D.A dedicated memory controller

💡 Difficulty: medium | ✅ Correct: C

📖 Explanation: Fine-grained multithreading requires specific hardware logic to manage the frequent, cycle-by-cycle switching between threads. This logic is not necessary for coarse-grained multithreading, where switches are infrequent and can be managed by simpler mechanisms.

Q39. What is the primary function of the thread-switching logic in the Intel Itanium processor?

A.To migrate software threads between cores

B.To decide which hardware thread to execute next ✅

C.To handle interrupts from I/O devices

D.To manage the processor's cache hierarchy

💡 Difficulty: medium | ✅ Correct: B

📖 Explanation: The Itanium's thread-switching logic compares the urgency values of the available hardware threads to make a scheduling decision. Its primary function is to select which of the two hardware-managed threads on a core will execute next when a triggering event occurs.

Q40. A system administrator is tuning a server with a 4-core, 8-thread processor (2 threads per core). The workload is a mix of many small I/O-bound threads and a few large CPU-bound threads. The administrator observes that the CPU-bound threads are not making good progress. What is the likely cause?

A.The I/O-bound threads are causing too many interrupts

B.The memory bus is saturated

C.The I/O-bound threads are consuming the hardware threads and causing the CPU-bound threads to be scheduled less often ✅

D.The CPU-bound threads have a very low priority

💡 Difficulty: hard | ✅ Correct: C

📖 Explanation: If there are many small, frequently running threads, they can occupy the hardware threads. On a system with 8 logical processors, if these threads are scheduled first, they may keep the cores busy. The large CPU-bound threads might be starved, as they may be scheduled less frequently, especially if the scheduler is fair.

Q41. The Intel Itanium uses an urgency value. Which of the following scenarios would most likely cause the core to switch from the current thread to another?

A.The current thread's urgency value increases

B.The current thread's stack overflows

C.A long-latency cache miss occurs on the current thread ✅

D.The operating system explicitly signals the core to switch

💡 Difficulty: hard | ✅ Correct: C

📖 Explanation: The Itanium switches when certain events occur. A long-latency event on the current thread, like a significant cache miss, would likely trigger the thread-switching logic. This logic would then compare urgency values and potentially select the other thread to execute while the current one is stalled.

Q42. Why is the issue of memory stalls more prominent in modern processors?

A.Because modern processors have smaller caches

B.Because modern processors are much faster than memory ✅

C.Because modern processors use slower memory modules

D.Because modern processors have fewer cores

💡 Difficulty: hard | ✅ Correct: B

📖 Explanation: Memory stall issues are amplified because the performance gap between processors and memory has widened. Processors have become significantly faster over the years, but memory speeds have not improved at the same rate. This makes the processor increasingly likely to be waiting for slower memory, leading to a higher percentage of stall cycles.

Q43. What is the relationship between 'hardware threads' and 'logical processors'?

A.They are the same concept, just viewed from different perspectives ✅

B.Hardware threads are a software concept, logical processors are a hardware concept

C.Hardware threads are the physical CPUs, logical processors are virtual

D.They are unrelated concepts

💡 Difficulty: medium | ✅ Correct: A

📖 Explanation: They are the same underlying concept. A 'hardware thread' is what the hardware provides, and a 'logical processor' is the operating system's perception of that hardware. Each hardware thread is presented as a separate logical processor to the OS.

🔗 Related Topics (MCQs)

📝 CPU Scheduling Basic Concepts MCQs 📝 CPU I/O Burst Cycle MCQs 📝 CPU Scheduler in Operating System MCQs 📝 Preemptive Scheduling in Operating System MCQs 📝 Dispatcher in CPU Scheduling MCQs

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