🏠 Home > An Introduction To Microprocessor 8085 > 5. The 8085 Microprocessor > Timing Diagram of MOV reg, M of 8085 Microprocessor
← Back to 5. The 8085 Microprocessor

📝 Timing Diagram of MOV reg, M of 8085 Microprocessor

📖 From An Introduction To Microprocessor 8085 • 5. The 8085 Microprocessor • 12 questions available

Practice MCQs for Timing Diagram of MOV reg, M of 8085 Microprocessor. Test your knowledge with carefully crafted questions across easy, medium, and hard difficulty levels.

🔄 Last updated: 2026-07-30

2
Easy Questions
6
Medium Questions
4
Hard Questions

📝 Sample Questions

Q1. An instruction MOV A, M reads the byte stored at the memory address held in the H‑L pair and loads it into the accumulator. If memory location 0x30 contains the value 0x5A, what will A contain after the instruction completes?

🔹 A. 90
🔹 B. 165
🔹 C. 0
🔹 D. 255

💡 Difficulty: easy | ✅ Correct: A

Q2. Why does the timing diagram for MOV reg, M show two distinct machine cycles?

🔹 A. The first cycle fetches the opcode, the second fetches the operand from memory.
🔹 B. The first cycle writes the result, the second clears the flags.
🔹 C. Both cycles are used to increment the program counter twice.
🔹 D. One cycle fetches the opcode and the other writes to the register file.

💡 Difficulty: medium | ✅ Correct: B

Q3. Why does the timing diagram of MOV reg, M show a high‑impedance (Z) state on the data bus during the opcode fetch cycle?

🔹 A. Because the memory is not driving the bus at that moment.
🔹 B. Because the CPU is waiting for an interrupt.
🔹 C. Because the address lines are being latched.
🔹 D. Because the data bus is reserved for future use.

💡 Difficulty: hard | ✅ Correct: A

⬆️ View all questions in the quiz below

🔗 Related Topics

📝 Architecture of 8085 Microprocessor📝 Register Section of 8085 Microprocessor📝 Address Buffer and Address Data Buffer of 8085 Microprocessor📝 Arithmetic and Logical Unit (ALU) of 8085 Microprocessor📝 Timing and Control Unit of 8085 Microprocessor
🚀 Start Quiz 📝 Practice Mode