📝 Delay Calculations for SAP II Computers

Q1. In which year was the Intel 4004 microprocessor released?

💡 Difficulty: easy | ✅ Correct: B

Q2. Why does increasing the word size generally reduce the number of memory accesses for a given data block?

💡 Difficulty: medium | ✅ Correct: A

Q3. A system designer estimates that the instruction fetch stage introduces a delay of \(30\text{ ns}\), decode stage \(20\text{ ns}\), execute stage \(40\text{ ns}\), and write‑back stage \(10\text{ ns}\). What is the total pipeline latency for one instruction?

💡 Difficulty: hard | ✅ Correct: A