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📝 Data Bus Buffer of 8257

📖 From An Introduction To Microprocessor 8085 • 12. Direct Memory Access Controller: 8257 • 8 questions available

Practice MCQs for Data Bus Buffer of 8257. Test your knowledge with carefully crafted questions across easy, medium, and hard difficulty levels.

🔄 Last updated: 2026-07-30

2
Easy Questions
4
Medium Questions
2
Hard Questions

📝 Sample Questions

Q1. What is the maximum number of DMA channels that the Intel 8257 controller can support?

🔹 A. 2
🔹 B. 4
🔹 C. 8
🔹 D. 16

💡 Difficulty: easy | ✅ Correct: B

Q2. A system using the 8257 sets the address register of channel 2 to 0x3000 and requests a transfer of 2000 bytes. Assuming the address increments after each byte, what address will the address register contain after the transfer completes?

🔹 A. 14288
🔹 B. 16000
🔹 C. 16384
🔹 D. 10752

💡 Difficulty: medium | ✅ Correct: A

Q3. During a DMA request, how does the 8257 coordinate bus arbitration with the CPU, and why is the acknowledge (ACK) signal critical?

🔹 A. The 8257 asserts HOLD, CPU releases buses, and ACK tells peripheral that transfer may begin
🔹 B. The 8257 directly controls the CPU clock, and ACK resets the CPU
🔹 C. The 8257 does not interact with the CPU; ACK is only for peripheral timing
🔹 D. The 8257 uses ACK to signal the end of the entire program

💡 Difficulty: hard | ✅ Correct: A

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🔗 Related Topics

📝 Block Diagram of 8257📝 DMA Channels of 8257📝 Read/ Write Logic of 8257📝 Control Logic of 8257📝 Mode Set Register of 8257
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